Text Box: IEEE International Workshop on Defect and Data Driven Testing (D3T-2009)  D3T-2009

 

Home

Call for Paper (pdf)

Paper Submission

ITC 2009

Final Program

Organizing/Program Committee

Registration (For workshop only or with ITC)

Hotel/Travel

 

Previous Events

DBT 2008

DBT 2007

DBT 2006

DBT 2005

DBT 2004

DBT 2000

Text Box: November 5-6, 2009 Austin Convention Center, TX

 

Submission Deadline (Extended): September 4, 2009

Notification of Acceptance: September 23, 2009

Camera Ready Paper: October 3, 2009

 

D3T-2009 will be held in conjunction with ITC 2009

 

 

 

 

As technology scales, various new types of defects are presenting unique challenges to the test community. New test defect and data based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-90nm technology nodes and their impact on product quality and in-field reliability. Defect and data-driven testing (D3T) has been in practice for a number of years and often used for yield learning and analysis. It is now gaining attention more than ever in production test. D3T uses data to reduce defect levels, increase reliability, and to diagnose and solve yield problems. D3T can provide feedbacks on which tests to add/remove, or test subsets. It can also be utilized for improving quality of logic test patterns vs. outlier analysis tests. However, test data has not been easily accessible by smaller companies and researchers in academia.

 

The IEEE International Workshop on Defect and Data-Driven Testing (D3T 2009) is aimed at addressing the above issues. Paper presentations on topics related to the topics listed below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

 

·  Outlier Identification

·  Data-Driven Testing (DDT)

·  Test Data Analysis

·  Yield Learning and Analysis Using DDT

·  Adaptive Test

·  Data-Mining Methods for Test Data Processing

·  Low Voltage Testing

·  Elevated Voltage Testing and Stress Testing

·  Reliability and Yield

·  Nanometer Test Challenges

·  Defect Coverage & Metrics

·  Mixed Current/Voltage Testing

·  Economics of Defect Based Testing

·  Fault Localization & Diagnosis

·  Noise and Crosstalk Testing

·  Transition and Delay Fault Testing

To present at the workshop, submit a PDF version of an extended abstract of at least 1000 words via Easy Chair by Sep. 4, 2009. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Oct. 3, 2009. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.

 

Technical Program Submissions:

Al Crouch

Asset-Intertech

E-mail: acrouch@asset-intertech.com

Visit our www site at: http://d3t.tttc-events.org/

 

General Information:

Mohammad Tehranipoor

University of Connecticut

E-mail: tehrani@engr.uconn.edu