Text Box: IEEE International Workshop on Defect and Data Driven Testing (D3T-2010)    D3T-2010

 

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Text Box: November 4-5, 2010 Austin Convention Center, TX

 

Submission Deadline : August 21, 2010

Notification of Acceptance: September 16, 2010

Camera Ready Paper: September 26, 2010

 

D3T-2010 will be held in conjunction with ITC 2010

 

 

 

 

As technology scales, various new types of defects are presenting unique challenges to the test community. New test defect and data based methodologies are required to detect, monitor, and comprehend the various defect mechanisms at sub-50nm technology nodes and their impact on product quality and in-field reliability. Defect and data-driven testing (D3T) has been in practice for a number of years and often used for yield learning and analysis. It is now gaining attention more than ever in production test. D3T uses data to reduce defect levels, increase reliability, and to diagnose and solve yield problems. D3T can provide the basis for Adaptive Test decisions on which test conditions, tests, or test subsets to add/remove, it can also be utilized for improving the overall quality of test by the use of outlier analysis. However, how to implement and analyze test and defect data in making these decisions is not a widely understood or utilized process in the industry. Closing the gap on knowledge of the process, new test techniques, and how defect models are being used to adapt test flows will be the goals of this year’s D3T workshop.

  

The IEEE International Workshop on Defect and Data-Driven Testing (D3T 2010) is aimed at addressing the above issues. Paper presentations on topics related to the topics listed below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

 

·  Outlier Identification

·  Data-Driven Testing (DDT)

·  Test Data Analysis

·  Yield Learning and Analysis Using DDT

·  Adaptive Test

·  Data-Mining Methods for Test Data Processing

·  Low Voltage Testing

·  Elevated Voltage Testing and Stress Testing

·  Reliability and Yield

·  Nanometer Test Challenges

·  Defect Coverage & Metrics

·  Mixed Current/Voltage Testing

·  Economics of Defect Based Testing

·  Fault Localization & Diagnosis

·  Noise and Crosstalk Testing

·  Transition and Delay Fault Testing

To present at the workshop, submit a PDF version of an extended abstract of at least 1000 words via Easy Chair by Aug. 21, 2010. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Sep. 26, 2010. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.

 

Technical Program Submissions:

Sankaran Menon

Intel Corp.

E-mail: Sankaran.Menon@intel.com

Visit our www site at: http://d3t.tttc-events.org/

 

General Information:

Al Crouch

Asset-Intertech

E-mail: acrouch@asset-intertech.com