D3T-2009

 

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Call for Paper (pdf)

Paper Submission

Final Program

ITC 2009

Organizing/Program Committee

Registration

Hotel/Travel

The IEEE International Workshop on

Defect and Data Driven Testing (D3T-2009)

 

Nov. 5 - 6, 2009 Austin Convention Center, TX

Will be held in conjunction with ITC Test Week (ITC-2009)

 

Previous Events

DBT 2008

DBT 2007

DBT 2006

DBT 2005

DBT 2004

DBT 2000

 

 

 

Final Program (pdf)

 

Day 1 - Thursday, Nov. 5

4:00pm - Opening Remarks:  M. Tehranipoor (Univ. of Connecticut)

 

4:10pm - 5:00 pm

Thursday Keynote: Design for Reality -- Validation of Timing Analysis with Test Measurements

                        Magdy Abadir (Freescale)

 

5:10pm - 6:30pm

Session 1: Statistical Analysis and Yield

Chair – Nisar Ahmed (Texas Instruments)

 

30: Manufacturing Processes for End-to-End Yield Optimization (Invited Talk)

            Matthias Kamm (Cisco)

30: Data in Culture of Zero Defects (Invited Talk)

            LeRoy (Freescale)

20: Rapid Yield Learning through Short Loop Electrical Fault Localization

            Jacob Orbon (Verigy)

 

Workshop Welcome Reception - 7:00pm - 9:00pm

 

Day 2 - Friday, Nov. 6

8:00am - 9:20 am

Tutorial: Data Collection and the New and Expanded STDF Format

Ajay Koche (Consultant)

 

9:30am - 10:30am

Session 2: Defect Based Testing

Chair – Kohei Miyase (KIT)

 

20: On-Chip Power Supply Noise Measurements   

 Ekarat Laohavaleeson and Chintan Patel (UMBC)

20: Verification of Convolution Relation between Sensitized Path’s Gate Transients, Power Grid Impulse Responses and Power Port Transients

Reza M. Rad (UMBC), Jim Plusquellic (UNM), Chintan Patel (UMBC) and Abhishek Singh (nVidia)

20: A mechanism to address di/dt noise during delay test

            Amitava Majumdar, Ramamurthy Setty, Yan Dong, Nehal Patel, Arani Sinha (AMD)

 

Coffee Break- 10:30am - 10:50am

 

10:50am - 11:50am

Session 3: Signal Integrity and Power-Aware Test

Chair – Sankaran Menon, Intel  

 

20: Extended Abstract: Developing a Novel Quality Metric for Path-Delay Fault Pattern Evaluation   

Junxia Ma, Jeremy Lee and Mohammad Tehranipoor (UConn)

20: Optimizing the Percentage of X-Bits to Reduce Switching Activity   

Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen and Seiji Kajihara (KIT)

20: Realistic Low Cost Framework for Supply Noise Aware Delay Test Compaction   

            Zhongwei Jiang, Zheng Wang, Jing Wang and D. M. H. Walker (Texas A&M)

 

Lunch - 11:50 pm - 1:00pm

 

1:00pm - 2:00pm

Session 4: Industry Practices

Chair – Hank Walker (Texas A&M)

 

30: Statistical Outlier Method Applications

Amit Nahar, Kenneth Butler, John Carulli and Charles Weinberger (Texas Instruments)

30: Title (Invited)

                        Anne Gattiker (IBM)

 

Short Break- 2:00 pm - 2:20pm

 

2:20pm - 4:00 pm - Panel Discussion

Test and Diagnosis for Parametric Failures

 

Organizers:

Mohammad Tehranipoor (UConn)

 

Panelists:

Michael Mateja, AMD

Al Crouch, Asset-Intertech

LeRoy Winemberg, Freescale

Srinivas Patil, Intel

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